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cy62137ev30 mobl ? 2-mbit (128 k 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05443 rev. *f revised november 8, 2012 2-mbit (128 k 16) static ram features very high speed: 45 ns wide voltage range: 2.20 v to 3.60 v pin compatible with cy62137cv30 ultra low standby power ? typical standby current: 1 ? a ? maximum standby current: 7 ? a ultra low active power ? typical active current: 2 ma at f = 1 mhz easy memory expansion with ce and oe features automatic power-down when deselected complementary metal oxide semiconductor (cmos) for optimum speed and power byte power-down feature offered in pb-free 48-ball very fine-pitch ball grid array (vfbga) and 44-pin thin small outline package (tsop ii) package functional description the cy62137ev30 is a high performance cmos static ram organized as 128k words by 16 bits. this device features advanced circuit design to provide ultra low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature that significantly reduces power consumption by 90% when addresses are not toggling. the device can also be put into standby mode reducing power consumption when deselected (ce high or both ble and bhe are high). the input and output pins (i/o 0 through i/o 15 ) are placed in a high impedance state when: deselected (ce high), outputs are disabled (oe high), both byte high enable and byte low enable are disabled (bhe , ble high), or during a write operation (ce low and we low). writing to the device is accomplished by asserting chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location spec ified on the address pins (a 0 through a 16 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 16 ). reading from the device is accomplished by asserting chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appears on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory appears on i/o 8 to i/o 15 . see the truth table on page 11 for a complete description of read and write modes. the cy62137ev30 is available in 48-ball vfbga and 44-pin tsopii packages. 128k x 16 ram array i/o 0 ? i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 i/o 8 ? i/o 15 ce we bhe a 16 a 0 a 1 a 9 power - down circuit bhe ble ce a 10 ble logic block diagram a 11
cy62137ev30 mobl ? document number: 38-05443 rev. *f page 2 of 18 contents pin configurations ........................................................... 3 product portfolio .............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 5 thermal resistance .......................................................... 5 ac test loads and waveforms ....................................... 5 data retention characteristics ....................................... 6 data retention waveform ................................................ 6 switching characteristics ................................................ 7 switching waveforms ...................................................... 8 truth table ...................................................................... 11 ordering information ...................................................... 12 ordering code definitions ..... .................................... 12 package diagrams .......................................................... 13 acronyms ........................................................................ 15 document conventions ................................................. 15 units of measure ....................................................... 15 document history page ................................................. 16 sales, solutions, and legal information ...................... 18 worldwide sales and design s upport ......... .............. 18 products .................................................................... 18 psoc solutions ......................................................... 18
cy62137ev30 mobl ? document number: 38-05443 rev. *f page 3 of 18 pin configurations figure 1. 48-ball vfbga (top view) [1, 2] figure 2. 44-pin tsop ii (top view) [1] we a 11 a 10 a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe vss a 7 i/o 0 bhe nc nc a 2 a 1 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc nc nc 3 2 6 5 4 1 d e b a c f g h a 16 nc vcc we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 v cc a 16 a 15 a 14 a 13 a 4 a 3 oe v ss a 5 i/o 15 a 2 ce i/o 2 i/o 0 i/o 1 bhe a 1 a 0 18 17 20 19 i/o 3 27 28 25 26 22 21 23 24 v ss i/o 6 i/o 4 i/o 5 i/o 7 a 6 a 7 ble v cc i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 i/o 8 a 8 a 9 a 10 a 11 a 12 nc nc product portfolio product v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( ? a) f = 1 mhz f = f max min typ [3] max typ [3] max typ [3] max typ [3] max cy62137ev30-45ll 2.2 v 3.0 v 3.6 v 45 ns 2 2.5 15 20 1 7 notes 1. nc pins are not connected on the die. 2. pins d3, h1, g2, h6 and h3 in the 48-ball vfbga package are addr ess expansion pins for 4 mb, 8 mb, 16 mb, and 32 mb and 64 mb respectively. 3. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25 c.
cy62137ev30 mobl ? document number: 38-05443 rev. *f page 4 of 18 maximum ratings exceeding the maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ............................... ?65 c to + 150 c ambient temperature with power applied ......................................... ?55 c to + 125 c supply voltage to ground potential ....................................?0.3 v to (v cc(max) + 0.3 v) dc voltage applied to outputs in high z state [4, 5] ...................?0.3 v to (v cc(max) + 0.3 v) dc input voltage [4, 5] ................?0.3 v to (v cc(max) + 0.3 v) output current into outputs (low) ............................. 20 ma static discharge voltage (per mil-std-883, method 3015) ......................... > 2001 v latch up current .................................................... > 200 ma operating range device range ambient temperature v cc [6] cy62137ev30-45ll industrial ?40 c to +85 c 2.2 v to 3.6 v electrical characteristics over the operating range parameter description test conditions 45 ns unit min typ [7] max v oh output high voltage i oh = ?0.1 ma v cc = 2.20 v 2.0 ? ? v i oh = ?1.0 ma v cc = 2.70 v 2.4 ? ? v v ol output low voltage i ol = 0.1 ma v cc = 2.20 v ? ? 0.4 v i ol = 2.1 ma v cc = 2.70 v ? ? 0.4 v v ih input high voltage v cc = 2.2 v to 2.7 v 1.8 ? v cc + 0.3 v v cc = 2.7 v to 3.6 v 2.2 ? v cc + 0.3 v v il input low voltage v cc = 2.2 v to 2.7 v ?0.3 ? 0.6 v v cc = 2.7 v to 3.6 v ?0.3 ? 0.8 v i ix input leakage current gnd < v i < v cc ?1 ? +1 ? a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 ? a i cc v cc operating supply current f = f max = 1/t rc v cc = v ccmax i out = 0 ma cmos levels ?1520ma f = 1 mhz ? 2.0 2.5 i sb1 [8] automatic ce power-down current ? cmos inputs ce > v cc ? ? 0.2 v or (bhe and ble ) > v cc ? ? 0.2 v, v in > v cc ? 0.2 v, v in < 0.2 v, f = f max (address and data only), f = 0 (oe and we ), v cc = 3.60 v ?17 ? a i sb2 [8] automatic ce power-down current ? cmos inputs ce > v cc ? 0.2 v or (bhe and ble ) > v cc ? ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = 3.60 v ?17 ? a notes 4. v il(min.) = ?2.0 v for pulse durations less than 20 ns. 5. v ih(max) = v cc + 0.75 v for pulse durations less than 20 ns. 6. full device ac operation assumes a 100 ? s ramp time from 0 to vcc(min) and 200 ? s wait time after v cc stabilization. 7. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25 c. 8. chip enable (ce ) and byte enables (bhe and ble ) need to be tied to cmos levels to meet the i sb1 / i sb2 / i ccdr specification. other inputs can be left floating.
cy62137ev30 mobl ? document number: 38-05443 rev. *f page 5 of 18 capacitance parameter [9] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf thermal resistance parameter [9] description test conditions 48-ball bga 44-pin tsop ii unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 75 77 ? c/w ? jc thermal resistance (junction to case) 10 13 ? c/w ac test loads and waveforms figure 3. ac test loads and waveforms v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: thvenin equivalent all input pulses r th r1 parameters 2.50 v 3.0 v unit r1 16667 1103 ? r2 15385 1554 ? r th 8000 645 ? v th 1.20 1.75 v note 9. tested initially and after any design or process changes that may affect these parameters.
cy62137ev30 mobl ? document number: 38-05443 rev. *f page 6 of 18 data retention characteristics over the operating range parameter description conditions min typ [10] max unit v dr v cc for data retention 1 ? ? v i ccdr [11] data retention current v cc = 1 v, ce > v cc ? 0.2 v or (bhe and ble ) > v cc ? ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v ?0.83 ? a t cdr [12] chip deselect to data retention time 0??ns t r [13] operation recovery time 45 ? ? ns data retention waveform figure 4. data retention waveform [14] v cc(min) v cc(min) t cdr v dr > 1.0 v data retention mode t r v cc ce or bhe .ble notes 10. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25 c. 11. chip enable (ce ) and byte enables (bhe and ble ) need to be tied to cmos levels to meet the i sb1 / i sb2 / i ccdr specification. other inputs can be left floating. 12. tested initially and after any design or proc ess changes that may affect these parameters. 13. full device operation requires linear v cc ramp from v dr to v cc(min.) > 100 ? s or stable at v cc(min.) > 100 ? s. 14. bhe .ble is the and of both bhe and ble . the chip can be deselected by either disabling the chip enable signals or by disabling both bhe and ble .
cy62137ev30 mobl ? document number: 38-05443 rev. *f page 7 of 18 switching characteristics over the operating range parameter [15, 16] description 45 ns unit min max read cycle t rc read cycle time 45 ? ns t aa address to data valid ? 45 ns t oha data hold from address change 10 ? ns t ace ce low to data valid ? 45 ns t doe oe low to data valid ? 22 ns t lzoe oe low to low z [17] 5?ns t hzoe oe high to high z [17, 18] ?18ns t lzce ce low to low z [17] 10 ? ns t hzce ce high to high z [17, 18] ?18ns t pu ce low to power-up 0 ? ns t pd ce high to power-down ? 45 ns t dbe ble /bhe low to data valid ? 45 ns t lzbe ble /bhe low to low z [17] 5?ns t hzbe ble /bhe high to high z [17, 18] ?18ns write cycle [19] t wc write cycle time 45 ? ns t sce ce low to write end 35 ? ns t aw address setup to write end 35 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 35 ? ns t bw ble /bhe low to write end 35 ? ns t sd data setup to write end 25 ? ns t hd data hold from write end 0 ? ns t hzwe we low to high z [17, 18] ?18ns t lzwe we high to low z [17] 10 ? ns notes 15. test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1v/ns) or less, ti ming reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ.) , and output loading of the specified i ol /i oh as shown in figure 3 on page 5 . 16. ac timing parameters are subject to byte enable signals (bhe or ble ) not switching when chip is disabled. refer application note, an13842 for more information. 17. at any given temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 18. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high impedance state. 19. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe and ble = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing should be referenced to the edge of the s ignal that terminates the write.
cy62137ev30 mobl ? document number: 38-05443 rev. *f page 8 of 18 switching waveforms figure 5. read cycle 1: address transition controlled [20, 21] figure 6. read cycle no. 2: oe controlled [21, 22] address data out previous data valid data valid t rc t aa t oha 50% 50% data valid t rc t ace t lzbe t lzce t pu data out high impedance impedance i cc i sb t hzoe t hzce t pd oe ce high v cc supply current t hzbe bhe /ble t lzoe address t dbe t doe notes 20. the device is continuously selected. oe , ce = v il , bhe and ble = v il . 21. we is high for read cycle. 22. address valid prior to or coincident with ce and bhe , ble transition low.
cy62137ev30 mobl ? document number: 38-05443 rev. *f page 9 of 18 figure 7. write cycle no. 1: we controlled [23, 24, 25] figure 8. write cycle no. 2: ce controlled [23, 24, 25] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t wc data i/o address ce we oe t hzoe data in note 26 bhe /ble t bw t sce t hd t sd t pwe t ha t aw t sce t wc t hzoe data in ce address we data i/o oe note 26 bhe /ble t bw t sa notes 23. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe and ble = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing should be referenced to the edge of the signal that terminates the write 24. data i/o is high impedance if oe = v ih . 25. if ce goes high simultaneously with we = v ih , the output remains in a high impedance state. 26. during this period, the i/os are in output state and input signals should not be applied.
cy62137ev30 mobl ? document number: 38-05443 rev. *f page 10 of 18 figure 9. write cycle no. 3: we controlled, oe low [27] figure 10. write cycle no. 4: bhe /ble controlled, oe low [27] switching waveforms (continued) data in t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 28 t bw bhe /ble data i/o address t sd t sa t ha t aw t wc ce we data in note 28 t bw bhe /ble t sce t pwe t hzwe t hd t lzwe notes 27. if ce goes high simultaneously with we = v ih , the output remains in a high impedance state. 28. during this period, the i/os are in output state and input signals should not be applied.
cy62137ev30 mobl ? document number: 38-05443 rev. *f page 11 of 18 truth table ce we oe bhe ble inputs/outputs mode power hxxx [29] x [29] high z deselect/power-down standby (i sb ) x [29] x x h h high z deselect/power-down standby (i sb ) l h l l l data out (i/o o ?i/o 15 ) read active (i cc ) lhlhldata out (i/o o ?i/o 7 ); i/o 8 ?i/o 15 in high z read active (i cc ) l h l l h data out (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z read active (i cc ) l h h l l high z output disabled active (i cc ) l h h h l high z output disabled active (i cc ) l h h l h high z output disabled active (i cc ) l l x l l data in (i/o o ?i/o 15 ) write active (i cc ) l l x h l data in (i/o o ?i/o 7 ); i/o 8 ?i/o 15 in high z write active (i cc ) l l x l h data in (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z write active (i cc ) note 29. chip enable (ce ) and byte enables (bhe / ble ) must be at fixed cmos levels (not floating). inte rmediate voltage levels on these pins is not permitted.
cy62137ev30 mobl ? document number: 38-05443 rev. *f page 12 of 18 ordering code definitions ordering information speed (ns) ordering code package diagram package type operating range 45 cy62137ev30ll-45bvxi 51-85150 48-ball vfbga (6 mm 8 mm 1 mm) (pb-free) industrial 45 cy62137ev30ll-45zsxi 51-85087 44-pin tsop ii (pb-free) temperature grade: i = industrial pb-free package type: xx = bv or zs bv = 48-ball vfbga zs = 44-pin tsop ii speed grade: 45 ns low power voltage range: 3 v typical process technology: 90 nm bus width = 16 density = 2-mbit family code: mobl sram family company id: cy = cypress cy -xx 621 3 7 e ll i 45 x v30
cy62137ev30 mobl ? document number: 38-05443 rev. *f page 13 of 18 package diagrams figure 11. 48-ball vfbga (6 8 1 mm) bv48/bz48 package outline, 51-85150 51-85150 *h
cy62137ev30 mobl ? document number: 38-05443 rev. *f page 14 of 18 figure 12. 44-pin tsop z44- ii package outline, 51-85087 package diagrams (continued) 51-85087 *e
cy62137ev30 mobl ? document number: 38-05443 rev. *f page 15 of 18 acronyms document conventions units of measure acronym description ble byte low enable bhe byte high enable ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory tsop thin small outline package vfbga very fine-pit ch ball gird array we write enable symbol unit of measure c degree celsius mhz megahertz ? a microampere ? s microsecond ma milliampere mm millimeter ns nanosecond % percent pf picofarad ? ohm v volt w watt
cy62137ev30 mobl ? document number: 38-05443 rev. *f page 16 of 18 document history page document title: cy62137ev30 mobl ? , 2-mbit (128 k 16) static ram document number: 38-05443 rev. ecn no. orig. of change submission date description of change ** 203720 aju see ecn new data sheet *a 234196 aju see ecn changed i cc max at f=1mhz from 1.7 ma to 2.0 ma changed i cc typ from 12 ma (35 ns speed bin) and 10 ma (45 ns speed bin) to 15 ma and 12 ma respectively changed i cc max from 20 ma (35 ns speed bin) and 15 ma (45 ns speed bin) to 25 ma and 20 ma respectively changed i sb1 and i sb2 typ from 0.6 ? a to 0.7 ? a changed i sb1 and i sb2 max from 1.5 ? a to 2.5 ? a changed i ccdr from 1 ? a to 2 ? a fixed typos on tsop ii pinout: pin 18-22: address lines pin 23: nc added pb-free information *b 427817 nxr see ecn converted from advanced information to final. removed 35 ns speed bin removed ?l? version changed ball e3 from dnu to nc. removed the redundant footnote on dnu. moved product portfolio from page # 3 to page #2. changed i cc (max) value from 2 ma to 2.5 ma and i cc (typ) value from 1.5 ma to 2 ma at f=1 mhz changed i cc (typ) value from 12 ma to 15 ma at f = f max =1/t rc changed i sb1 and i sb2 typ. values from 0.7 ? a to 1 ? a and max. values from 2.5 ? a to 7 ? a. changed v cc stabilization time in footnote #7 from 100 ? s to 200 ? s changed the ac test load capacitance from 50pf to 30pf on page# 4 changed v dr from 1.5v to 1v on page# 4. changed i ccdr from 2 ? a to 3 ? a. added i ccdr typical value. corrected t r in data retention characteristics from 100 ? s to t rc ns changed t oha , t lzce and t lzwe from 6 ns to 10 ns changed t lzbe from 6 ns to 5 ns changed t lzoe from 3 ns to 5 ns changed t hzoe, t hzce, t hzbe and t hzwe from 15 ns to 18 ns changed t sce, t aw and t bw from 40 ns to 35 ns changed t pwe from 30 ns to 35 ns changed t sd from 20 ns to 25 ns updated the ordering information table and replaced the package name column with package diagram. *c 2604685 vkn / pyrs 11/12/08 added footnote 8 related to i sb2 and i ccdr added footnote 13 related to ac timing parameters *d 3143896 rame 01/17/2011 added acronyms and units of measure table added ordering code definitions added toc converted all tablenote to footnotes updated package diagrams 51-85150 from *d to *f *e 3283711 aju 06/15/2011 removed the note ?for best practice recommendations, refer to the cypress application note ?sram system design guidelines? on http://www.cypress.com .? and its reference in functional description . updated in new template.
cy62137ev30 mobl ? document number: 38-05443 rev. *f page 17 of 18 *f 3806123 tava 11/08/2012 updated data retention waveform (updated figure 4 (changed ?v dr > 1.5 v? to ?v dr > 1.0 v?)). updated package diagrams (spec 51-85150 (changed revision from *f to *h), spec 51-85087 (changed revision from *c to *e)). document history page (continued) document title: cy62137ev30 mobl ? , 2-mbit (128 k 16) static ram document number: 38-05443 rev. ecn no. orig. of change submission date description of change
document number: 38-05443 rev. *f revised november 8, 2012 page 18 of 18 all products and company names mentioned in this document may be the trademarks of their respective holders. cy62137ev30 mobl ? ? cypress semiconductor corporation, 2004-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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